Chevin Technology was established as an electronic engineering design consultancy in 2003 in Cambridge, UK. In 2011, Chevin Technology opened its Yorkshire office and began creating Ethernet IP Cores for Xilinx FPGAs in house, whilst continuing with design consulting. Chevin Technology is now primarily a specialist Ethernet IP Core provider, offering expert support and design services.
In 2018 Chevin Technology relocated back to Cambridge, and is now located at The Bradfield Centre, Cambridge Science Park. Chevin Technology is one of few vendors offering high performance, reliable Ethernet IP Cores for high end FPGAs. A broad range of engineering expertise and IP Core development experience allows Chevin Technology to offer a great blend of stability and flexibility to our customers.
At Chevin Technology, we have designed our Ethernet IP Cores to smooth the way for simple integration of FPGAs into our clients' products, while supporting the highest of performance standards. Customers choose Chevin Technology's products because they benefit from high performance IP Cores with responsive, expert support and design services at competitive prices.
In 2018 Chevin Technology relocated back to Cambridge, and is now located at The Bradfield Centre, Cambridge Science Park. Chevin Technology is one of few vendors offering high performance, reliable Ethernet IP Cores for high end FPGAs. A broad range of engineering expertise and IP Core development experience allows Chevin Technology to offer a great blend of stability and flexibility to our customers.
At Chevin Technology, we have designed our Ethernet IP Cores to smooth the way for simple integration of FPGAs into our clients' products, while supporting the highest of performance standards. Customers choose Chevin Technology's products because they benefit from high performance IP Cores with responsive, expert support and design services at competitive prices.
Services
Achieve optimal data transfer time on your FPGA using the 10GLLMAC/PCS, an IP stack that combines Chevin Technology's Ultra Low- Latency 10-Gbit/s Ethernet XG MAC, and XG PCS/PMA IP cores.
Contact us for a free evaluation of the fast packet round trip time of 160 ns on your Virtex or Kintex UltraScale FPGA.
Contact us for a free evaluation of the fast packet round trip time of 160 ns on your Virtex or Kintex UltraScale FPGA.
When combined with the Ultra Low-Latency XGPCS, the full packet round trip time ( MAC Input -> Wire -> MAC Output ) is 153.8ns in 5153 LUTs.
We understand that efficiency is crucial to our customers, and have created a powerful CRC32 checker & generator engine that checks the TX and RX data for errors, on a 64bit wide bus @ 156.25MHz.
Latency of the XGMAC can be reduced even further by the use of Cut-through mode; the first byte appears only 19 nanoseconds after arriving at XGMII.
Alternatively, the Store-and-Forward mode reduces application workload, as the XGMAC drops all corrupt frames.
We understand that efficiency is crucial to our customers, and have created a powerful CRC32 checker & generator engine that checks the TX and RX data for errors, on a 64bit wide bus @ 156.25MHz.
Latency of the XGMAC can be reduced even further by the use of Cut-through mode; the first byte appears only 19 nanoseconds after arriving at XGMII.
Alternatively, the Store-and-Forward mode reduces application workload, as the XGMAC drops all corrupt frames.
User Datagram Protocol (UDP/IP) is a communications protocol used for establishing connections between applications on the Internet.
The UDP Protocol is a transport layer that runs on top of the Internet Protocol (IP) Layer and is used for connections where high sustained throughput is a priority and some data loss is expected, such as with video and audio streaming.
Chevin Technology's 10G & 25G UDP Ethernet IP core for FPGAs has low latency and bandwidth overhead, as it sends packets of data without confirming receipt.
The UDP Protocol is a transport layer that runs on top of the Internet Protocol (IP) Layer and is used for connections where high sustained throughput is a priority and some data loss is expected, such as with video and audio streaming.
Chevin Technology's 10G & 25G UDP Ethernet IP core for FPGAs has low latency and bandwidth overhead, as it sends packets of data without confirming receipt.
The TCP/IP (Transmission Control Protocol/ Internet Protocol) is an Ethernet IP stack for FPGAs that incorporates both the transport and internet layer protocols to deliver reliable, end to end network communications using the internet or on private networks.
The TCP/ IP stack can be used with Chevin Technology's 10G & 25G Ethernet IP cores for dependable, low-latency connectivity in any FPGA using a minimum of FPGA resources.
Chevin Technology's TCP/IP Offload Engine is an FPGA Synthesisable Ethernet TCP/IP server/client in a lean and fast, all-RTL solution.
The TCP/ IP stack can be used with Chevin Technology's 10G & 25G Ethernet IP cores for dependable, low-latency connectivity in any FPGA using a minimum of FPGA resources.
Chevin Technology's TCP/IP Offload Engine is an FPGA Synthesisable Ethernet TCP/IP server/client in a lean and fast, all-RTL solution.
At Chevin Technology, we offer our customers expert engineering design services that are flexible, cost effective and well supported.
Customers can gain a project based, off-site addition to their engineering team, or receive ad hoc expert consultation to suit their business needs.
Responsive communication is readily available using Skype, telephone and email.
Typically, consultation with Chevin Technology begins with a clear definition and agreement of project specifications and work packages, followed by weekly status reports to ensure that project milestones are achieved and challenges communicated in an efficient and timely manner.
Customers can gain a project based, off-site addition to their engineering team, or receive ad hoc expert consultation to suit their business needs.
Responsive communication is readily available using Skype, telephone and email.
Typically, consultation with Chevin Technology begins with a clear definition and agreement of project specifications and work packages, followed by weekly status reports to ensure that project milestones are achieved and challenges communicated in an efficient and timely manner.
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